{"id":17036,"date":"2024-07-03T13:17:07","date_gmt":"2024-07-03T05:17:07","guid":{"rendered":"https:\/\/aiportek.com\/?page_id=17036"},"modified":"2024-07-03T15:02:06","modified_gmt":"2024-07-03T07:02:06","slug":"irigtimem-irig-b-slave-ip-core","status":"publish","type":"page","link":"https:\/\/aiportek.com\/en\/irigtimem-irig-b-slave-ip-core\/","title":{"rendered":"IRIGtimeS: IRIG-B slave IP core"},"content":{"rendered":"
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IRIGtimeS<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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IRIG-B slave IP core\n<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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IRIGtimeS implements an IRIG 200-04-compatible time synchronization slave on an FPGA device. This IRIG-B slave IP core has been designed to support all IRIG-B encoding expressions as well as DCLS and AM modulation to provide maximum flexibility.<\/p>

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This IRIG-B slave IP core receives IRIG-B frames per second and obtains time information (seconds, minutes, hours, days, years, control functions, and binary continuous seconds) based on IRIG-B time code. The IP implements a 64-bit internal timer to provide time stamps (in seconds) and nanosecond values. The timer values and frequencies are synchronized with the received IRIG-B time information. The IP is designed to provide autonomous operation, requiring as little configuration as possible.<\/p>

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IRIGtimeS supports the following Xilinx FPGA families:<\/p>

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