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10M/100M/1G MES – 網管以太網交換機IP核

Product Overview

網管以太網交換機 (MES) 是一種以太網交換機 IP 內核,面向可編程硬件平台,如FPGA和可重新配置的SoC。

 

該IP具有非阻塞交叉矩陣,允許在所有端口之間進行連續傳輸。實施存儲轉發交換方法,交換機在轉發之前緩沖並驗證每個幀。此外,延遲時間為納秒級。因此,ME S是實現基於以太網的工業網絡的完美交換機。

 

此外,它還可以用於其他應用程序。由於采用了FPGA技術,我們的 IP 內核具有高度可配置性,提供了廣泛的選項。在這種情況下,我們的 MES IP Core 可以從簡單的3 端口 以太網交換機變為具有 QoS 和 RSTP 的 32 端口以太網交換機。

 

MES 可以與 SoC-e 的 IP 核結合使用,在所需的端口中引入 HSR 和 PRP 功能。HSR 切換方法是Cut Through。因此,該組合提供了最大的性能和與標準的兼容性。

connector

  • 全雙工或半雙工以太網接口(高達 1Gbps)
  • Half-duplex 10/100 Mbps Ethernet interface
  • 10 Gbps以太網接口
  • Configurable 3 to 32 Ethernet ports
  • MII/RMII/GMII/RGMII/SGMII/QSGMII/USXGMII Physical Layer Device (PHY) Interface
  • Each port supports different data rates
  • Copper and fiber media interfaces: 10/100/1000Base-T, 100Base-FX, 1000Base-X

exchange

  • 動態或靜態 MAC 表(最多 4096 個條目)
  • Giant Frame Management
  • Ethernet-based switching
  • Entrance Port Mirror
  • 廣播/組播風暴防護
  • Rate limiting per port (broadcast, multicast and unicast traffic)
  • configure
  • MDIO、UART、AXI4-Lite 或 CoE(以太網配置)
  • 購買 IP 核時提供驅動程序

Time Synchronization

  • IEEE 1588v2 stateless transparent clock function (P2P-Layer 2/E2E-Layer 2)
  • 兼容SoC-e IEEE 1588 IP核(1588Tiny,精確時間基礎)
  • Distribution management
  • 組播幀過濾
  • Switching Port Mask: User-defined frame forwarding to specific ports.
    Port-based VLAN support
  • 服務質量(QoS)
    優先級(PCP-802.1p,DSCP TOS,以太類型)
  • IEEE 802.1X EAPOL hardware processing
  • DSA(分布式交換結構)

Redundancy Agreement

  • RSTP (requires software stack)
    Hardware Support for RSTP
    IP核隨附的用於Linux的參考RSTP堆棧
    Provides Posix-compatible RSTP stacks
  • MRP (no software stack)
    環形管理員(MRM)
    Ring Client (MRC)
  • DLR (no software stack)
    Beacon based nodes
    Supervisor Node

支持的 Xilinx FPGA 系列和評估板

我們的 MES IP 核可部署在以下 Xilinx 系列中。您可以在以下鏈接中找到不同的 Xilinx 產品表和選擇指南:

 

7-Series

Ultrascale

Ultrascale+

Versal ACAP

 

Refer to the boards supported by the design:

exist評估板方面,我們還推出了系統級模塊( SoM ),可以提供預加載的 IP 內核設計。在這種情況下,我們建議使用SMARTzynq 砖解決方案,它具有7 系列 Zynq Xilinx FPGA。如果 7 系列 Zynq 器件不是您想要的,我們還有其他基於 Ultrascale 或 Ultrascale+ Xilinx FPGA 系列的 SoM。

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Time Sensitive Networking (TSN) is a new generation of network technology based on the evolution of the standard Ethernet architecture. It takes traditional Ethernet as the network foundation and provides a data link layer protocol specification for deterministic data transmission capability through mechanisms such as clock synchronization, data scheduling, and network configuration. Compared with traditional Ethernet, TSN can provide microsecond-level deterministic services, reduce the complexity of the entire communication network, and realize the convergence of information technology (IT) and operation technology (OT). With its precise clock synchronization, deterministic traffic scheduling, and intelligent and open operation and maintenance management framework, TSN can ensure the high-quality transmission of multiple business traffic in a common network, and it has both performance and cost advantages, and it is the development trend of the future network. This is the future trend of network development.

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