Supports industrial Ethernet, automotive switched Ethernet, time-triggered Ethernet, and AFDX with arbitrary speeds and topologies;

Supports worst-case analysis and timing-accurate simulation of heterogeneous communication architecture consisting of CAN, switched Ethernet, AFDX, FlexRay, LIN and ARINC429 buses interconnected via gateways;

Generative design using ZeroConfig-TSN (ZCT) - a "push-button" method of automatically selecting and configuring a TSN network;

NEW: The Topology Stress Test (TST) design space exploration algorithm helps designers make early topology and technology choices without fully understanding the communication requirements;

Higher level communication layers, runtime environments and applications can be modeled using user-written Java plug-ins. In this way, complete embedded systems can be simulated;

Optimized TSN Time-Aware Shaper for Interconnected Networks (IEEE 802.11Qbv) Transmission Timing;

Supports Kalray MPPA and many of STMicroelectronics' core architectures for on-chip networking;

Analyze and configure task scheduling, event-triggered and time-triggered scheduling, stand-alone tasks, tasks depicted as graphs and runnable objects, validation of system-wide timing chains across tasks, networks and CPUs;

The latest techniques for implementing network calculus to calculate upper bounds on communication latency, frame jitter, and buffer utilization;

Provides worst-case analysis and time-accurate simulation through a parallelized simulation engine to predict worst-case scenarios and typical performance;

Supports FIFO, priority, AVB credit-based shaper, TSN time-aware shaper, frame grabber, TTEthernet and polling frame scheduler;

Includes optimized priority assignment and routing algorithms, as well as configuration algorithms for AVB credit-based formers and TSN time-aware formers;

Supports periodic and sporadic message transfer modes, UDP and TCP transfers, segmented messages (e.g., video streams and FTP traffic), and overlay transfer modes (e.g., DoIp protocol);

Rich graphical versions and visualization environments with communication architecture editor, Gantt chart and design options comparison;

Easily import and export network configurations and simulation results via Java export plug-ins, CSV, XML files, and industry-common formats;

For true worst-case delays, the maximum pessimism of the calculated communication delay is limited (typically less than 15%) and is evaluated for each data stream;

This includes NETAIRBENCH, a benchmark test generator that creates random and realistic Ethernet configurations for early evaluation or to study how the network will adapt to more loads in the future;

The analysis is fast, analyzing large AFDX networks in civil aircraft in less than 10 seconds;

Runs on all 32 or 64 bit platforms that support Java - no dongle or license server protection;

Professional support and custom extensions are available. It is also possible to use the RTaW-Pegase functionality via the Software Developer SDK for use in your own programs.