The 10G Managed Ethernet Switch (MES) IP core features a full-speed, HOL-free arbitrary cross-matrix for continuous transmission between all ports. It supports up to 32 ports with different line speeds. The switch employs a store-and-forward methodology to fully satisfy the Ethernet standard policy regarding frame integrity checks.

The internal microarchitecture includes destructive enhancements to ensure reliable switch operation even in critical use cases. For example, the mirrored MAC tables of the virtual output queue combinations allow simultaneous access to the matrix at maximum data throughput. the IP does not require any external storage.

The 10G MES is a multi-speed (100M/1G/2.5G/5G/10Gs) switch IP with support for the IEEE 1588 V2 transparent clock feature. This feature modifies PTP event messages and takes into account the time spent traveling through the switch. The solution improves distribution accuracy by compensating for delivery variations across the network. Specifically, 10G MES also supports IEEE 1588 V2 One Step Transparent Clock Peering (P2P) by allowing each port to use independent hardware. This feature compensates not only for dwell time, but also for the latency of each link.

The IP includes MII/GMII/RGMII native interfaces for Ethernet PHY devices and can be combined with Xilinx IP to support interfaces such as RMII/SGMIIQ/SGMII and USXGMII. It also provides an AXI4-Stream interface to simplify connectivity to other IP cores such as SAS crypt for wire-speed security.

10G managed Ethernet switch IP core for Xilinx Vivado tools.

The 10G managed Ethernet switch IP is fully integrated on the Xilinx Vivado IPI tool. The graphical interface allows configuration of common parameters of the IP from a high-level view. Due to this flexibility at synthesis time, it is feasible to obtain an optimized implementation in terms of functions and ports for a given application and device. In addition, the IP can be directly instantiated using any HDL language.